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Website: http://www.arithmatica.com/

Arithmatica is the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for math-intensive ICs, such as those used in 3D graphics, imaging, multimedia, wireline and wireless communications, and embedded processing. Its unique technology, available through its tools products and design services, provides differentiated improvement to...More»

Address: 2033 Gateway Place, 5th Floor San Jose, CA 95110 Map it »

Phone: 408-573-5999

Founded: 1998

Industry: Computer Hardware and Electronics

Sub-Industry: Semiconductors

Legal Structure: Corporation

Ownership: Private

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Name:	CellMath Designer
Product URL:	http://www.arithmatica.com/products/cellmathdesigner.html
Description:	As your IC designs migrate to 65 nm and beyond, optimizing datapath designs for power, area and timing becomes critical due to the exponential increase in leakage currents and the skyrocketing cost of silicon and IC packaging. Implementing datapath designs manually or by using generic logic synthesis tools just won’t produce the power, area and timing results that you need to be successful at 65 nm. Your IC designers need a powerful solution that’s focused specifically on optimizing datapath designs and that’s what you get from Arithmatica. CellMath Designer is a powerful yet affordable datapath synthesis tool that will amaze you with its high quality of results and ease of use. Quality of Results CellMath Designer delivers the industry’s most advanced and comprehensive algorithms and heuristics for power, area and timing optimization of datapaths. Using its RTL transformation technology, CellMath Designer automatically creates an optimal internal representation of your design for datapath synthesis. Then by successively applying algorithms for architectural selection, mux synthesis, pipelining/retiming and logic optimization/mapping, CellMath Designer automatically produces the best gate-level implementation possible based on the design constraints specified. Standard Interfaces and Libraries CellMath Designer is easy to implement because it supports standard Verilog inputs and outputs, synthesis library formats (.lib) and scripting language (TCL). It’s a complete solution that seamlessly plugs into your existing Cadence, Synopsys or Magma flow. Ease of Use CellMath Designer provides automatic partitioning of the datapath section of your RTL models, freeing your IC designers from the task of manually dissecting their designs. Your IC designers control CellMath Designer using a familiar scripting language (TCL), so their learning curve is short. CellMath Designer also produces gate-level models fully compatible with Cadence and Synopsys formal verification tools (Conformal, Formality) and simulators (VCS, NC-Sim) so your engineers can complete their design cycles easily and quickly.
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