Founded in 2004, the idea that led to the company’s inception came from the founders’ experiences developing a full gate-level hardware implementation of the TCP/IP protocol stack to create a 1Gbps transport offload engine (TOE). Although successful, that endeavor made it clear that the next step in performance, 10Gbps, for a full stack TOE would require a radically new approach to IC design that could accelerate both the design creation and the functional verification steps of the process. With that as its charter, CebaTech developed the C2R Compiler™, the first system-level design tool to unify design modeling, architecture exploration, verification and implementation in a single design methodology capable of supporting full-chip designs. Today, in addition to the C2R Compiler, CebaTech licenses C2R Compiler — generated IP blocks to hardware developers in high-growth markets, with an initial focus on high-performance IP for the fast evolving storage and networking markets.
|07/01/06||Series C||4M||2M Technology Ventures, SAS Investors, NJTC Venture Fund||Unknown|