Inovys Overview
Inovys Corporation was founded to support the semiconductor industry's move to Design For Test (DFT) with practical, economic, and scalable structured logic testing solutions. By offering a new generation of test system and software products, Inovys provides substantial cost advantages when testing complex SoC's that incorporate DFT. The most significant benefits are lower testing costs, quicker...More»
Inovys Corporation was founded to support the semiconductor industry's move to Design For Test (DFT) with practical, economic, and scalable structured logic testing solutions. By offering a new generation of test system and software products, Inovys provides substantial cost advantages when testing complex SoC's that incorporate DFT. The most significant benefits are lower testing costs, quicker test development efforts, and rapid feedback to design teams. With industry leading solutions for larger volume scan patterns, delay fault testing, BIST, and embedded memory, Inovys' innovative test systems address the test challenges of SoC, ASIC, datacomm, DSP, microprocessor, microcontroller, and other complex devices.«Less
Key People
Management
- Colin Ritchie, VP Marketing
- Ric Dokken, VP Engineering
- Phil Burlison, CTO
- Kurt Johnson, VP Finance
- Tommie Berry, VP of Product Development
- Rob Bisaillon, VP Operations
- Paul Sakamoto, President/CEO
- David Bayly, VP Sales & Field Operations
- Phuong Quach, VP Finance
- Clyde Armstrong, President
- Al Crouch, Chief Scientist
Board of Directors
Funding
| Date | Type | Capital Amount | Post-Money Valuation | Investors |
|---|---|---|---|---|
| 02/04/2004 | Series C | 16.3M | Unknown |
Products
| Name: | Personal Ocelot |
| Product URL: | http://www.inovys.com/p/p.aspx?mlid=13 |
| Description: | • Debug and structurally validate first silicon in minutes • Slice weeks from production test program development • Quickly characterize frequency performance with AC Scan • Most comprehensive desktop system for silicon validation. New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on efficient test systems. The Personal Ocelot is the first effective desktop validation system for semiconductor IC development. Now verification, product and test engineers can refine and release their engineering samples and test codes from their office or lab. It offers extensive capabilities for testing complex IC devices including ATPG-based scan and BIST that incorporate DFT. Faster Debug and Validation of Engineering Samples Now you can use scan test to track silicon failures back to individual flipflops, instead of getting the cycle and pin of the first failure. The Personal Ocelot operating system is designed to support STIL and uses STIL-based files unchanged (like the ATPG output from Cadence Encounter, Mentor Graphics FastScan, and Synopsys TetraMAX). Since these files contain all the necessary flipflop names and chain links of the device's scan chains, the Personal Ocelot can immediately identify failing flipflop and pattern failures. Faster Production Test Program Development The Personal Ocelot can quickly develop vectors and test programs without taking a production tester offline. Because the Personal Ocelot and the Ocelot use the same operating system, they can use the same program development and characterization tools. The Personal Ocelot can also debug and diagnose chips that have failed on a production tester. Time can also be significantly reduced to track yield impacts such as erroneous masks, load boards, test environment setting and improper or varying process parameters or defect content. Quickly Isolate Speed Defects Using AC Scan The Personal Ocelot's High Performance Clock Channels allow you to perform AC testing to 400MHz (or even higher when internal PLL's are used during scan capture cycles). Transition Delay and Path Delay patterns can be used in conjunction with the Personal Ocelot's evaluation tools to quickly isolate areas where speed performance is a problem. Eliminate the Design to Test Bottleneck Stylus® is a software operating system that is based on the IEEE1450 standard (STIL). This platform provides a seamless, bidirectional interface between the ATE, EDA and DFT worlds. It can directly read timing and pattern files generated by commercial ATPG and BIST tools from Cadence, Mentor Graphics, Synopsys and others. • Up to 256 general-purpose I/O pins • 32MB of real-time measurement fail/data capture memory per pin • Dynamic Data Matrix™ maximizes flexibility of Pattern Memory (up to 16 billion pin vectors of Pattern Memory is equal to 64M vectors times 256 pins) • Per-pin timing and formatting • 50MHz data rates • 400MHz clock channels for precise transition and path delay measurements • DC parametric measurement units (PMUs) • Programmable power supplies • Stylus™ Operating System (based on IEEE1450) – Same Software as the Ocelot |
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